module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);

    always @(posedge clk) begin
        if(reset) begin
            q <= 0;
        end
        else if(q < 9) begin
            q <= q + 1;
        end
        else begin
            q <= 0;
        end
    end

    // always @ (posedge clk)
    //     begin
    //         if(reset)
    //             q <= 4'b0000;
    //         else if(q <= 4'b1000)
    //             q <= q + 1'b1;
    //         else
    //             q <= 4'b0000;
    //     end 

    // always @(posedge clk)
	// 	if (reset || q == 9)	// Count to 10 requires rolling over 9->0 instead of the more natural 15->0
	// 		q <= 0;
	// 	else
	// 		q <= q+1;

endmodule
